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Integrated Circuit Systems, Inc.
ICS85310I-31
LOW SKEW, DUAL, 1-TO-5 2.5V/3.3V DIFFERENTIAL-TO-ECL/LVPECL FANOUT BUFFER
FEATURES
* 2 differential 2.5V/3.3V LVPECL / ECL bank outputs * 2 differential clock input pairs * CLKx, nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL * Maximum output frequency: 700MHz * Translates any single ended input signal to 3.3V LVPECL levels with resistor bias on nCLKx input * Output skew: 25ps (typical) * Part-to-part skew: 270ps (typical) * Propagation delay: 1.7ns (typical) * LVPECL mode operating voltage supply range: VCC = 2.375V to 3.8V, VEE = 0V * ECL mode operating voltage supply range: VCC = 0V, VEE = -3.8V to -2.375V * -40C to 85C ambient operating temperature
GENERAL DESCRIPTION
The ICS85310I-31 is a low skew, high performance dual 1-to-5 Differential-to-2.5V/3.3V ECL/LVPECL HiPerClockSTM Fanout Buffer and a member of the HiPerClockSTM family of High Performance Clock Solutions from ICS. The CLKx, nCLKx pairs can accept most standard differential input levels. The ICS85310I-31 is characterized to operate from either a 2.5V or a 3.3V power supply. Guaranteed output and part-to-part skew characteristics make the ICS85310I-31 ideal for those clock distribution applications demanding well defined performance and repeatability.
,&6
BLOCK DIAGRAM
CLKA nCLKA QA0 nQA0 QA1 nQA1 CLK_ENA D Q LE QA2 nQA2 QA3 nQA3 QA4 nQA4
PIN ASSIGNMENT
nQA0 nQA1 nQA2 VCCO VCCO
32 31 30 29 28 27 26 25 VCC CLK_ENA CLKA nCLKA CLK_ENB CLKB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
VCCO nQB4 QB4 nQB3 QB3 nQB2 QB2 VCCO
ICS85310I-31
QA0
QA1
QA2
24 23 22 21 20 19 18 17
QA3 nQA3 QA4 nQA4 QB0 nQB0 QB1 nQB1
CLKB nCLKB
QB0 nQB0 QB1 nQB1
nCLKB VEE
CLK_ENB
D Q LE
QB2 nQB2 QB3 nQB3 QB4 nQB4
32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View
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REV. C JULY 31, 2003
Integrated Circuit Systems, Inc.
ICS85310I-31
LOW SKEW, DUAL, 1-TO-5 2.5V/3.3V DIFFERENTIAL-TO-ECL/LVPECL FANOUT BUFFER
Type Power Unused Input Input Unused Input Input Power Power Output Output Output Output Output Output Output Output Output Output Pullup Pullup Pullup Pullup Description Core supply pin. Synchronizing clock enable. LVCMOS/LVTTL interface levels. Inver ting differential clock input. Synchronizing clock enable. LVCMOS/LVTTL interface levels. Inver ting differential clock input. Negative supply pin. Output supply pins. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Pulldown Non-inver ting differential clock input.
TABLE 1. PIN DESCRIPTIONS
Number 1 2 3 4 5 6 7 8 9, 16, 25, 32 10, 11 12, 13 14, 15 17, 18 19, 20 21, 22 23, 24 26, 27 28, 29 30, 31 Name VCC CLK_ENA CLKA nCLKA CLK_ENB CLKB nCLKB VEE VCCO nQB4, QB4 nQB3, QB3 nQB2, QB2 nQB1, QB1 nQB0, QB0 nQA4, QA4 nQA3, QA3 nQA2, QA2 nQA1, QA1 nQA0, QA0
Pulldown Non-inver ting differential clock input.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF K K
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ICS85310I-31
LOW SKEW, DUAL, 1-TO-5 2.5V/3.3V DIFFERENTIAL-TO-ECL/LVPECL FANOUT BUFFER
Outputs QA0:QA4, QB0:QB4 Disabled; LOW nQA0:nQA4, nQB0:nQB4 Disabled; HIGH
TABLE 3A. CONTROL INPUT FUNCTION TABLE
Inputs CLK_ENA, CLK_ENB 0
1 Enabled Enabled After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1. In the active mode, the state of the outputs are a function of the CLKA, nCLKA and CLKB, nCLKB inputs as described in Table 3B.
Disabled
CLKA, nCLKB CLKA, CLKB
Enabled
CLK_ENA, CLK_ENB
nQA0:nQA4, nQB0:nQB4 QA0:QA4, QB0:QB4
FIGURE 1. CLK_EN TIMING DIAGRAM
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs CLKA or CLKB 0 1 0 1 Biased; NOTE 1 Biased; NOTE 1 nCLKA or nCLKB 1 0 Biased; NOTE 1 Biased; NOTE 1 0 1 QA0:QA4, QB0:QB4 LOW HIGH LOW HIGH HIGH LOW Outputs nQA0:nQA4, nQB0:nQB4 HIGH LOW HIGH LOW LOW HIGH Input to Output Mode Differential to Differential Differential to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Polarity Non Inver ting Non Inver ting Non Inver ting Non Inver ting Inver ting Inver ting
NOTE 1: Please refer to the Application Information "Wiring The Differential Input To Accept Single Ended Levels".
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ICS85310I-31
LOW SKEW, DUAL, 1-TO-5 2.5V/3.3V DIFFERENTIAL-TO-ECL/LVPECL FANOUT BUFFER
4.6V -0.5V to VCC + 0.5V 50mA 100mA 47.9C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC, VCCO = 2.375V to 3.8V, TA = -40C to 85C
Symbol VCC VCCO IEE Parameter Core Supply Voltage Output Supply Voltage Power Supply Current Test Conditions Minimum 2.375 2.375 Typical 3.3 3.3 Maximum 3.8 3.8 120 Units V V mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC, VCCO = 2.375V to 3.8V, TA = -40C to 85C
Symbol Parameter VIH VIL IIH IIL Input High Voltage Input Low Voltage Input High Current Input Low Current CLK_ENA, CLK_ENB CLK_ENA, CLK_ENB CLK_ENA, CLK_ENB CLK_ENA, CLK_ENB VCC = VIN = 3.8V VCC = 3.8V, VIN = 0V -150 Test Conditions Minimum 2 -0.3 Typical Maximum VCC + 0.3 0.8 5 Units V V A A
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC, VCCO = 2.375V to 3.8V, TA = -40C to 85C
Symbol IIH IIL VPP Parameter Input High Current Input Low Current CLKA, CLKB nCLKA, nCLKB CLKA, CLKB nCLKA, nCLKB Test Conditions VCC = VIN = 3.8V VCC = VIN = 3.8V VCC = 3.8V, VIN = 0V VCC = 3.8V, VIN = 0V -5 -150 0.15 1.3 Minimum Typical Maximum 150 5 Units A A A A V
Peak-to-Peak Input Voltage
VCMR Common Mode Input Voltage; NOTE 1, 2 VEE + 0.5 VCC - 0.85 V NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for CLKA, nCLKA and CLKB, nCLKB is VCC + 0.3V.
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ICS85310I-31
LOW SKEW, DUAL, 1-TO-5 2.5V/3.3V DIFFERENTIAL-TO-ECL/LVPECL FANOUT BUFFER
Test Conditions Minimum VCCO - 1.4 VCCO - 2.0 0.6 Typical Maximum VCCO - 1.0 VCCO - 1.7 1.0 Units V V V
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC, VCCO = 2.375V to 3.8V, TA = -40C to 85C
Symbol Parameter VOH VOL VSWING Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50 to VCCO - 2V.
TABLE 5. AC CHARACTERISTICS, VCC, VCCO = 2.375V to 3.8V, TA = -40C to 85C
Symbol fMAX Parameter Output Frequency Propagation Delay; NOTE 1 Output Skew; NOTE 2, 4 Par t-to-Par t Skew; NOTE 3, 4 Output Rise Time Output Fall Time 20% to 80% 20% to 80% 200 200 500MHz 1.7 25 270 Test Conditions Minimum Typical Maximum 700 2.2 50 550 700 700 53 Units MHz ns ps ps ps ps %
tPD tsk(o) tsk(pp)
tR tF
odc Output Duty Cycle 47 All parameters measured at 500MHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
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ICS85310I-31
LOW SKEW, DUAL, 1-TO-5 2.5V/3.3V DIFFERENTIAL-TO-ECL/LVPECL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
2V
VCC, VCCO
Qx
SCOPE
VCC
nCLKA, nCLKB
LVPECL
nQx CLKA, CLKB
V
PP
Cross Points
V
CMR
VEE
V EE
-1.8V to -0.375V
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx PART 1 Qx nQy PART 2 Qy
nQx Qx nQy Qy
tsk(pp)
tsk(o)
PART-TO-PART SKEW
OUTPUT SKEW
80% Clock Outputs
80% VSW I N G
nCLKA, nCLKB CLKA, CLKB nQAx, nQBx QAx, QBx
tPD
20% tR tF
20%
OUTPUT RISE/FALL TIME
nQA0:nQA4, nQB0:nQB4 QA0:QA4, QB0:QB4
Pulse Width t
PERIOD
PROPAGATION DELAY
odc =
t PW t PERIOD
odc & tPERIOD
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ICS85310I-31
LOW SKEW, DUAL, 1-TO-5 2.5V/3.3V DIFFERENTIAL-TO-ECL/LVPECL FANOUT BUFFER APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VCC
R1 1K Single Ended Clock Input
CLKx
V_REF
nCLKx
C1 0.1u
R2 1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive
Zo = 50 5 2 Zo FOUT Zo = 50 50 FOUT 50 VCC - 2V FIN FIN Zo = 50
50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
3.3V 5 2 Zo
RTT =
1 (VOH + VOL / VCC -2) -2
Zo
FIGURE 3A. LVPECL OUTPUT TERMINATION
85310AYI-31
RTT
Zo = 50 3 2 Zo 3 2 Zo
FIGURE 3B. LVPECL OUTPUT TERMINATION
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ICS85310I-31
LOW SKEW, DUAL, 1-TO-5 2.5V/3.3V DIFFERENTIAL-TO-ECL/LVPECL FANOUT BUFFER
ground level. The R3 in Figure 4B can be eliminated and the termination is shown in Figure 4C.
TERMINATION FOR 2.5V LVPECL OUTPUTS
Figure 4A and Figure 4B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to
2.5V 2.5V VCCO=2.5V R1 250 Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R2 62.5 R4 62.5 R3 250
2.5V VCCO=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50
R3 18
FIGURE 4A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 4B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V VCCO=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50
FIGURE 4C. 2.5V LVPECL TERMINATION EXAMPLE
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LOW SKEW, DUAL, 1-TO-5 2.5V/3.3V DIFFERENTIAL-TO-ECL/LVPECL FANOUT BUFFER
here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 4A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation.
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 5A to 5E show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested
3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R2 50 R3 50 LVPECL HiPerClockS Input R1 50 R2 50 Zo = 50 Ohm nCLK HiPerClockS Input CLK
FIGURE 5A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN ICS HIPERCLOCKS LVHSTL DRIVER
BY
FIGURE 5B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVPECL R1 84 R2 84 HiPerClockS Input R4 125
3.3V 3.3V LVDS_Driv er R1 100 Zo = 50 Ohm Zo = 50 Ohm
CLK
nCLK
Receiv er
FIGURE 5C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
FIGURE 5D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVDS DRIVER
BY
3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 R3 125 R4 125 CLK Zo = 50 Ohm C2 nCLK HiPerClockS Input
R5 100 - 200
R6 100 - 200
R1 84
R2 84
R5,R6 locate near the driver pin.
FIGURE 5E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER WITH AC COUPLE
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LOW SKEW, DUAL, 1-TO-5 2.5V/3.3V DIFFERENTIAL-TO-ECL/LVPECL FANOUT BUFFER POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS85310I-31. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS85310I-31 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.8V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 3.8V * 120mA = 456mW Power (outputs)MAX = 30.94mW/Loaded Output pair If all outputs are loaded, the total power is 10 * 30.94mW = 309.4mW
Total Power_MAX (3.8V, with all outputs switching) = 456mW + 309.4mW = 765.4mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.765W * 42.1C/W = 117.2C. This is below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE qJA
FOR
32-PIN LQFP, FORCED CONVECTION
qJA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W
200
55.9C/W 42.1C/W
500
50.1C/W 39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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3. Calculations and Equations.
ICS85310I-31
LOW SKEW, DUAL, 1-TO-5 2.5V/3.3V DIFFERENTIAL-TO-ECL/LVPECL FANOUT BUFFER
LVPECL output driver circuit and termination are shown in Figure 6.
VCCO
Q1
VOUT RL 50 VCCO - 2V
Figure 6. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CCO
*
For logic high, VOUT = V (V
CC_MAX
OH_MAX
=V
CCO_MAX
- 0.935V
-V
OH_MAX
) = 0.935V =V - 1.67V
*
For logic low, VOUT = V (V
CCO_MAX
OL_MAX
CCO_MAX
-V
OL_MAX
) = 1.67V
Pd_H = [(V
OH_MAX
- (V
CCO_MAX
- 2V))/R ] * (V
L
CCO_MAX
-V
OH_MAX
) = [(2V - (V
CCO_MAX
-V
OH_MAX
))/R ] * (V
L
CCO _MAX
-V
OH_MAX
)=
[(2V - 0.935V)/50] * 0.935V = 19.92mW
Pd_L = [(V
OL_MAX
- (V
CCO_MAX
- 2V))/R ] * (V
L
CCO_MAX
-V
OL_MAX
) = [(2V - (V
CCO_MAX
-V
OL_MAX
))/R ] * (V
L
CCO_MAX
-V
OL_MAX
)=
[(2V - 1.67V)/50] * 1.67V = 11.02mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.94mW
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LOW SKEW, DUAL, 1-TO-5 2.5V/3.3V DIFFERENTIAL-TO-ECL/LVPECL FANOUT BUFFER RELIABILITY INFORMATION
TABLE 7. JAVS. AIR FLOW TABLE
qJA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W
200
55.9C/W 42.1C/W
500
50.1C/W 39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS85310I-31 is: 1216
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LOW SKEW, DUAL, 1-TO-5 2.5V/3.3V DIFFERENTIAL-TO-ECL/LVPECL FANOUT BUFFER
PACKAGE OUTLINE - Y SUFFIX
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 e L q ccc 0.45 0 --0.05 1.35 0.30 0.09 MINIMUM NOMINAL 32 --1.40 0.37 -9.00 BASIC 7.00 BASIC 5.60 Ref. 9.00 BASIC 7.00 BASIC 5.60 Ref. 0.80 BASIC 0.60 --0.75 7 0.10 1.60 0.15 1.45 0.45 0.20 MAXIMUM
Reference Document: JEDEC Publication 95, MS-026
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LOW SKEW, DUAL, 1-TO-5 2.5V/3.3V DIFFERENTIAL-TO-ECL/LVPECL FANOUT BUFFER
Marking ICS85310AI-31 ICS85310AI-31 Package 32 lead LQFP 32 lead LQFP on Tape and Reel Count 250 per tray 1000 Temperature -40C to 85C -40C to 85C
TABLE 9. ORDERING INFORMATION
Part/Order Number ICS85310AYI-31 ICS85310AYI-31T
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 85310AYI-31
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LOW SKEW, DUAL, 1-TO-5 2.5V/3.3V DIFFERENTIAL-TO-ECL/LVPECL FANOUT BUFFER
REVISION HISTORY SHEET
Rev A A A B
Table
Page 9
Description of Change Added Termination for LVPECL Outputs. Updated par t number from ICS85310-31 to ICS85310I-31 throughout the data sheet to reflect operating temperature. Corrected Marking from ICS85310AYI-31 to ICS85310AYI31. Power Supply table - increased max. value for IEE to 120mA from 30mA max.
Date 5/30/02 7/24/02 7/25/02 10/23/02
T9 T4A T2 T4D
14 4 10 2 4 5 8&9
C
Power Considerations have re-adjusted to the increased IEE value. Pin Characteristics Table - changed 4pF max. to 4pF typical. Updated Absolute Maximum Ratings. LVPECL DC Characteristics Table - changed VSWING from 0.85V max. to 1.0V max. Application section added, Termination for 2.5V LVPECL Outputs and Differential Clock Input Interface. 10 & 11 Power Considerations - recalculated Total Power Dissipation for 3.8V. 14 Ordering Information Table - corrected marking from ICS85310AYI31 to ICS85310AI-31.
7/31/03
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